Computer-Aided Formal Verification of Power Electronics Circuits (bibtex)

by OA Beg, L Nguyen, A Davoudi and Taylor T. Johnson

Reference:

OA Beg, L Nguyen, A Davoudi and Taylor T. Johnson, "Computer-Aided Formal Verification of Power Electronics Circuits", In VDE Frontiers in Analog Computer Aided Design (FAC'17), VDE, pp. 21–26, 2017.

Bibtex Entry:

@inproceedings{beg2017fac,
  title = {Computer-Aided Formal Verification of Power Electronics Circuits},
  author = {OA Beg and L Nguyen and A Davoudi and Taylor T. Johnson},
  year = {2017},
  month = jul,
  booktitle = {VDE Frontiers in Analog Computer Aided Design (FAC'17)},
  pages = {21--26},
  publisher = {VDE},
  publabel = {OC5},
  pubtype = {OC},
  pdf = "research/beg2017fac.pdf",
}